YAN Hui1, 2, 3, HU Yong-hui1, 2, HOU Lei1, 2
(1. National Time Service Center, Chinese Academy of Sciences, Xi′an 710600, China;
2. Key Laboratory for Precision Navigation and Timing Technology, National Time Service Center,
Chinese Academy of Sciences, Xi′an 710600, China;
3. Graduate University of Chinese Academy of Sciences, Beijing 100039, China)
Abstract: According to the advantage of the stable transfer delay of E1 interface, the time keeping module which can trace to the time of GPS System is proposed. The time information combination is given in order to adapt to the no framed transfer method for E1 interface. By using the HDB3 code as the transmission code and adopting the EP2C8T144I8 FPGA chip, the key time synchronous system module of E1 interface is designed. The simulations of the key modules are conducted and the results indicate that all the key modules meet the requirements of the time synchronization system.
Key words: time synchronization; E1 interface; HDB3 code; FPGA