Design and simulation of an IIR filter based on FPGA

JIAO Ming-tao^1,2,3, HUA Yu^1,2, OU YANG Di-bao⁴, GUO Wei^1,2

(1. National Time Service Centre, Chinese Academy of Sciences, Xi′an 710600, China;

2. Key Laboratory of Precision Navigation and Timing Technology, Nation Time Service Center,

Chinese Academy of Sciences, Xi′an 710600, China;

3. Graduate University of Chinese Academy of Sciences, Beijing 100039, China;

4. Communication College of Xi′an Sciences and Technology University, Xi′an 710054, China)

Abstract: Based on an analysis of the structure of IIR filter and with the help of Matlab, we accomplished and fulfilled a design of cascade type IIR filter based on the FPGA. At the same time, we designed and produced the vector file (.vec file), and completed the simulation of vector file in Quartus II. The simulation showed that the design of IIR filter can filter more efficiently, and the simulation ability of FPGA can be enhanced through the stimulation of vector file.

Key words: IIR Filter; FPGA(field programmable gate array); .vec File; Simulation