Print LIU Xiao-hua1,2,3, XU Lin-sheng1,3, HUA Yu1,3
(1. National Time Service Center, Chinese Academy of Sciences, Xi′an 710600, China;
2. Graduate University of Chinese Academy of Science, Beijing 100039, China;
3. Key Laboratory of Precision Navigation and Timing Technology, National Time Service Center,
Chinese Academy of Sciences, Xi′an 710600, China)
Abstract: A design of portable low frequency time-code receiver based on FPGA(field programmable gate array) is introduced. The receiver is characterized by small volume and low power consumption, and it is very convenient to carry it outdoors. The design of hardware structure and software algorithm is described in this paper. The chip of EP2C70F672C8 produced by the ALTERA company is adopted in the hardware structure, and the software design is completed in Quartus Ⅱ environment. The experimental results indicate that this receiver has merits such as high integrity level, good reliability, and being easy to be expanded and upgraded. Thus this receiver is of certain practical value.
Key words: low frequency time-code; digital receiver; digital filter; field programmable gate array(FPGA)