Application of CPLD to frequency synthesizer circuit of atomic clock

YAN Shi-dong¹, SUN Bing-feng^1,2, ZHONG Da¹, MEI Gang-hua¹

(1. The Key Laboratory of Atomic Frequency Standard of Chinese Academy of Sciences,

Wuhan Institute of Physics and Mathematics of Chinese Academy of Sciences, Wuhan 430071, China;

2. Graduate University of Chinese Academy of Sciences, Beijing 100039, China)

Abstract: A digitalization project is introduced aimming at the circuit-module of passive rubidium atomic frequency standard(RAFS). The circuit-module consisted of a 9-multiple frequency-selective amplification analog circuits and a 5.312 5 MHz synthesizer circuit constituted by a great deal of audions and molectrons. In the new digitalization project, the frequency multiplication from 10 MHz to 180 MHz can be realized accurately by using a complex programmable logic devices(CPLD) to control the phase lock loop(PLL), and a 5.312 5 MHz frequency synthesis is completed by using the inner “virtual” integration circuits of the CPLD. The practice has proved that it is easy to realize integration and easy to debug for this design scheme. After the digital circuit replaced the original circuits in the RAFS, the whole loop-lock can be realized and the performances are better than before, therefore the RAFS unit have made an important step toward digitalization and miniaturization.

Key words: rubidium atomic frequency standard; frequcompletedency synthesizer; complex programmable logic devices(CPLD); phase lock loop(PLL); field programmable gate array(FPGA)