Design and Implementation of a RS Decoder

Based on Altera’s IP Core

LIU Xue1,2, SU Jian-feng1, SUN Ting3

(1. National Time Service Center, Chinese Academy of Sciences, Xi’an 710600, China;

2. Graduate University of Chinese Academy of Sciences, Beijing 100039, China;

3. Xidian University, Xi’an 710071, China) 

Abstract: This paper introduces an Altera’s Reed-Solomon IP core to achieve the RS decoding function, and the method is characterized by short development cycle, low cost and reliability. This paper analyzes the principle of Altera company’s IP core, parameter configuration and interface designing, and verifies the correctness of the design through the timing simulation. This design method has been successfully applied to the data demodulation of BPL long wave receiver module.

Key words: RS code; IP core; FPGA(field programmable gate array)