Design and Implementation of Viterbi Decoder Based on FPGA for UWB

WANG Chao-gang1,2，LU Xiao-chun1　

(1. National Time Service Center, Chinese Academy of Sciences, Xi’an 710600, China;

 2. Graduate University of Chinese Academy of Sciences, Beijing 100039, China)

Abstract: Since it is very important to lower the error rate of the transition data in indoor navigation systems based on UWB technology, and a convolution encoder and a Viterbi decoder in channel coding are employed to control the error rate in the IEEE 802.15.3a protocol, a parallel Viterbi decoder has been designed and implemented, for which a constraint length of 7 and a trace back depth of 64 have been achieved. The design has been synthesized in Xilinx ISE 9.2 and simulated in Modelsim 6.0. The simulation results indicate that the design can match the request of the UWB system.

Key words: ultra wideband(UWB); add-compare-select unit; Viterbi decoder; field programmable gate array(FPGA)