XIE Liang1, 2, LU Xu1, 2, WU Cheng-ying3, YANG Jian-qing1,2, FAN Zhan-you1
(1. National Time Service Center, Chinese Academy of Sciences, Xi′an 710600, China;
2. Graduate University of Chinese Academy of Sciences, Beijing 100039, China;
3. Hubei University for Nationalities, En′shi 445000, China)
Abstract: For satisfying the engineering needs, a phase locked loop frequency synthesizer with high stability and low phase noise is designed and implemented based on the phase locked loop chip ADF4360-8.The design principle, hardware constitution, software design and the implementation are described. Some main chips and the key circuits are introduced with emphasis. The amplitude of 100 MHz output signal for the frequency synthesizer reaches 2.16 V(peak-peak), being able to directively drive the TTL circuit. The test results show that the output signals of the frequency synthesizer are characterized by good stability, low noise and high amplitude.
Key words: frequency synthesizer; phase locked loop; phase noise; VCO
