WANG Li-min^1,3, HU Yong-hui^1,2, HOU Lei^1,2, LIU Jun-liang^1,2,3

(1. National Time Service Centre, Chinese Academy of Sciences, Xi′an 710600, China;

2. Graduate University of Chinese Academy of Sciences, Beijing 100039, China;

3. Key Laboratory of Precision Navigation and Timing Technology, National Time Service Center,

Chinese Academy of Sciences, Xi′an 710600, China)

Abstract: IRIG-B code is an universal format of time code in the world and is widely used in timing systems. According to the characteristics of IRIG-B code modulation, a decoding plan based on FPGA is introduced with emphases on how to extract the synchronous second signal accurately from the synchronous timing sequency and how to get the time information included in the B code. The whole project is designed by using Verilog HDL and has been implemented successfully with the results shown.